Nanoscale control of domain walls by magnetic inhibitors

In an article published on ACS Nano, researchers at the Max Planck Institute of Microstructure Physics demonstrate a novel type of device, called local magnetic inhibitor, that allows for the manipulation of magnetic domain walls at the nanoscale, enabling new types of spintronic devices for memory, logic, and neuromorphic applications.

The information bits that flow in today's electronic devices such as computers and smartphones are stored in memories based on the local accumulation of electrons. These memories are rather inefficient because they must be constantly powered to avoid erasing data, and are physically separated from the central processing unit (CPU), which means that information must be continuously transferred between the memory and the CPU. Spintronic applications using nanowire "racetrack" devices, in which the bits of information are stored as magnetic domains separated by domain walls, promise to solve both problems. First, these magnetic devices are non-volatile, meaning that they can hold information for several years without the need for electrical power. Second, the domain walls can be efficiently moved along racetracks by very short current pulses, enabling a mix of memory and computing capabilities. Thus, the implementation of racetrack devices in conventional electronics would enable faster and more energy-efficient memories with superior properties and functionality. In this context, scientists at the Max Planck Institute of Microstructure Physics have recently demonstrated the realization of electrically readable nanoscopic racetracks [1], as well as novel devices to reduce the relative distance between domain walls, thereby increasing the information density [2].

In a recently published paper in ACS Nano, scientists provide a solution to precisely control the domain walls at the nanoscale. In addition, this publication demonstrates a useful tool for fabricating superior spintronic devices, with unconventional properties and advanced functionality. The researchers introduced a local magnetic inhibitor, a magnet of nanoscopic dimensions that can be patterned directly on top of racetrack nanowires. The inhibitor generates a local magnetic field that interacts with the domain walls, stopping or promoting their motion, just as two magnets can attract or repel each other. In this work, scientists demonstrate the use of magnetic inhibitors to precisely and selectively control the position of domain walls in the racetrack.

In addition, researchers exploit the fact that the inhibitor acts as a filter for domain walls of opposite configurations (namely, ↑↓ or ↓↑) to create logic gate operators. The magnetic field generated by the inhibitor allows one type of domain wall to pass, while it stops the opposite type, effectively filtering it out. Hence, a device based on controlling the magnetic inhibitor orientation (↑ or ↓) and the domain wall configuration in a racetrack (↑↓ or ↓↑) can operate as an XNOR logic gate. This opens the door to a new type of spintronic logic device, with active reconfigurability.

Finally, scientists at the Max Planck Institute used micromagnetic simulations to demonstrate that the magnetic inhibitor on a racetrack can mimic the properties of a neuron. The simulations show that when a domain wall is injected below the inhibitor, the magnetic field drives the domain wall back to its initial position. Conversely, if several consecutive current pulses continuously “push” the domain wall, this can eventually overcome the inhibitor. These features correspond to the leaky-integrate-and-fire functionality of neurons. The results add the racetrack-inhibitor device to those that can facilitate the realization of neuromorphic and unconventional computing.

This work was funded by the Samsung Electronics R&D program “Material and Device Research on Racetrack Memory”, and by the Fraunhofer - Max Planck cooperation program in the “Joint Initiative for Research and Innovation” (“Pakt für Forschung und Innovation”/project RASCAL).

[1] https://www.mpi-halle.mpg.de/multicore-memristor-from-electrically-readable-nanoscopic-racetracks
[2] https://pubs.acs.org/doi/10.1021/acsnano.4c02024