Multicore memristor from electrically readable nanoscopic racetracks

Beyond CMOS - non-binary multicore memory element from nanoscopic racetrack

The domain wall (DW)-based devices are highly promising for advanced memory as well as logic applications [1]. These innately spintronic devices rely on the current-induced motion of domain walls (CIDWMs), the data bits, along magnetic nanowire conduits, often referred to as “racetracks”. It has shown that spin-orbit torque (SOT), which are derived from spin currents generated by the conversion of charge currents injected into a spin Hall layer (typically heavy metal – e.g., Pt, W, Ta) adjacent to perpendicularly magnetized racetracks, can be highly efficient in moving the DWs in these racetracks when these DWs are chiral with a Néel structure. Typically, the motion of the DW can be detected optically – e.g., Kerr microscope. However, for applications, it is essential to detect such CIDWM electrically. In this study, we demonstrate the electrical tracking of multiple mobile domain walls in nanoscopic magnetic wires or racetracks using a set of specially engineered anomalous Hall detectors integrated into the racetracks - with a spatial resolution of better than 40 nm. We show that individual domain walls can be deterministically positioned at artificial pinning sites that are spaced at deep sub-micron distances from each other. Furthermore, we introduce two novel approaches to analyze the time-series signals from racetrack devices - static and dynamic phase space analyses (Poincaré plots for DW motion) - with which we show the dynamics of the domain wall motion over long periods of operation can be easily understood and visualized. These, in principle, could be used as general platforms for write error rate, which is one of the most important factors for the commercialization, in non-binary type memories in which the time-series signal is analogue-like. Electrical time-series signals from the Hall detectors allow for the static and dynamic phase space visualization, serially or concurrently, of the dynamics of a domain wall or multiple domain walls and are described by a multi-core memristor model. An important finding is that the domain wall dynamics and stochasticity can be readily controlled in racetracks with deep sub-micron dimensions. These findings are of key significance for advancing the racetrack’s performance as well as for advanced functionalities.

What comes next?

Over the 5 years of intense research collaboration with Samsung electronics, we have achieved important milestones to realize energy efficient and high bit-density racetrack memory [2- 4]. We now plan to achieve large-scale array-type racetrack memory device to confirm the performance. Furthermore, we are excited to explore non-binary device concepts using racetrack memory such as neuromorphic and probabilistic bit (P-bit) computing technologies.

[1] S. S. P. Parkin, M. Hayashi, L. Thomas, Magnetic domain-wall racetrack memory. Science 320, 190–194 (2008). [Fulltext]
[2] P. Wang, et al., Giant Spin Hall Effect and Spin–Orbit Torques in 5d Transition Metal–Aluminum Alloys from Extrinsic Scattering. Adv. Mat. 34, 2109406 (2022). [Fulltext]
[3] J. Yoon, S.-H. Yang, J.-C. Jeon, A. Migliorini, I. Kostanovskiy, T. Ma, S. S. P. Parkin, Local and global energy barriers for chiral domain walls in synthetic antiferromagnet–ferromagnet lateral junctions. Nat. Nanotechnol. 17, 1183-1191 (2022). [Fulltext]
[4] J.-C. Jeon, A. Migliorini, L. Fischer, J. Yoon, S. S. P. Parkin, Dynamic Manipulation of Chiral Domain Wall Spacing for Advanced Spintronic Memory and Logic Devices. ACS Nano 18, 14507-14513 (2024). [Fulltext]